1. Field of the Invention
The present invention generally relates to analog-to-digital (A/D) converter circuits for converting analog input signals into digital output signals. More particularly, the invention relates to an A/D converter that reduces the conversion deviation of a voltage comparison circuit, which would otherwise cause problems when the A/D converter is formed into an integrated circuit.
2. Description of the Related Art
Among the conversion methods used for A/D converters for converting analog input values into digital output values, a method, which is referred to as the "parallel (flash) conversion method" is known. In this method, a common analog input signal is input in parallel into a plurality of voltage comparators having different respective reference voltages, thereby instantaneously comparing the analog input value with the respective reference voltages. Upon comparison, the logical outputs (1 or 0) of the voltage comparators are then coded in binary form and are output.
The above flash conversion method is suitable for digitizing signals which have been sampled with a high sampling rate. On the other hand, this method requires as many voltage comparators as the number of conversion steps, i.e., the number of quantizing steps. The voltage comparator is, in general, a circuit that compares an input voltage with a reference voltage and then outputs the logical level 1 or 0. When such voltage comparators are formed into an integrated circuit, the uniformity of the voltage comparators is very difficult to achieve. A slight deviation of an input voltage from the reference voltage may sometimes change the output of the voltage comparator from logical 1 to logical 0 and vice versa. Accordingly, the width of a quantizing step cannot be set to be smaller than the above deviation threshold, which limits the conversion precision.
In order to solve the above problem concerning the deviation of outputs of voltage comparators, flash A/D converters aimed at improved conversion precision by utilizing the Hoashi & Millman's theorem (Ichiro Sakakigome, University Course Electric Circuit (1), Ohmsha, Ltd. 1996, pp. 126-127) are conventionally proposed. As an example of the above converters, the technique disclosed in the following technical document is known: K. Kattman, J. Barrow, "A technique for reducing differential nonlinearity errors in flash A/D converters", ISSCC Digest of Technica. Papers, pp. 170-171, February 1991 (hereinafter document (1)). In this technique, the above theorem is realized by arranging a plurality of voltage comparators in parallel in order of their reference voltages and by connecting the output terminals of adjacent voltage comparators to each other via resistors. With this configuration, the comparator outputs are added and averaged, thereby reducing the conversion deviations.
The technique disclosed in document (1) is further improved by the following technical document: K. Bult, A. Buchwald, J. Laskowski, "A 170 mW 10b 50M Sample/s CMOS ADC in 1 mm.sup.2 ", ISSCC Digest of Technical Papers, pp. 136-137, February 1997 (hereinafter document (2)). In technique, a plurality of flash A/D converters are used so that outputs of a plurality of comparators are averaged more precisely, thereby further enhancing the conversion precision.
It has been reported that the above improved flash A/D converters disclosed in document (2) effectively obtained a conversion precision on the order of 10 bits with a sampling rate of 50 MHz even when it was formed into a CMOS LSI circuit. This indicates that the error of the conversion precision of the voltage comparator is as low as 1 mV with respect to the input voltage. It is thus shown that the above technique is effective at improving the conversion precision.
However, it is difficult to obtain a conversion precision higher than the above level by the known A/D converters. For example, analog signals which require a higher sampling rate, such as RF signals, cannot be directly converted into digital signals for the following reason.
As noted above, known A/D converters are merely configured in such a manner that a plurality of voltage comparators are arranged in parallel and the output terminals of adjacent voltage comparators are connected to each other via resistors. Thus, the degree of contribution of one comparator to the output of another comparator is inversely proportional to the distance between the comparators. Accordingly, the degree of contribution between the comparators positioned farther away from each other is smaller. Thus, even if the outputs of such comparators are averaged, the conversion precision fails to be sufficiently improved.
Moreover, in known A/D converters, an output of the comparator positioned at the center is influenced by substantially the same number of both comparators located at the upper side having reference voltages higher than the center comparator and comparators located at the lower side having reference voltages lower than the center comparator. However, concerning the peripheral comparators, the influence of contributions from the other comparators is biased to either the higher reference voltage or the lower reference voltage. This drawback is more noticeable for the comparators located farther away from the center comparator. Consequently, depending on the input voltage value, outputs of the contributing comparators may be biased by a positive value or a negative value, thereby apparently changing the reference voltages of the peripheral comparators. This further lowers the integral nonlinearity, which is used as an index of performance of A/D converters.